1. Field of the Invention
The present invention relates to downsizing of hardware of a semiconductor integrated circuit, and more particularly to downsizing of a logic block of a semiconductor integrated circuit in a pipeline structure.
2. Description of the Background Art
FIG. 20 shows a general pipeline structure for pipeline processing. In FIG. 20, pipeline registers 1 and 2 are connected at the input side and output side of a logic circuit (hereinafter called logic block) 3 for performing logic action. The pipeline registers 1 and 2 are composed of flip-flops, and a clock signal CLK is given to them. Such a method of using the flip-flops as the registers, and controlling the logic action by the timing of providing the flip-flops with the edge of clock signal is called the edge trigger clock system. Herein, in a rear stage of the pipeline register 2, a logic block 4 is connected, which operates differently from the logic block 3, but hereinafter the composition of one logic block and two registers enclosing them is called one unit of pipeline, and one unit is described below.
FIG. 21 shows a block diagram of constitution of the logic block 3. The logic block 3 is a section for terminating a series of logic actions in one period of logic signal. The logic block 3 comprises logic means A, logic means B, and logic means C which perform different logic actions, being arranged in the sequence of A, B, A, C through signal lines b, c, d. In the logic block 3, an input signal given from the pipeline register 1 passes sequentially through the logic means A and logic means B in the first half of the clock signal, and passes sequentially through the logic means A and logic means C in the second half. FIG. 21 shows the passing route of the input signal by arrow. In this way, the logic block 3 has two logic means A identical in logic action, and the input signal passes through the logic means A in both first half and second half of the clock signal, and the same logic action is executed.
In the logic block of the conventional pipeline, as described herein, to repeat the same logic action in the first half and second half of the clock signal, it requires as many compositions as the number of repetitions. Especially for the purpose of numerical calculations such as an adder and multiplier, the same operation is often repeated regularly, and a plurality of operation circuits in the composition of performing the same logic action are required. In such a case, usually, the hardware becomes larger in size because the operation circuit of the same composition is increased in plural positions.